Electrically alterable read only memory semiconductor device made by low pressure chemical vapor deposition process

ABSTRACT

An electrically alterable read only memory (EAROM) having a tunneling layer of an insulating material such as silicon dioxide which is grown on the substrate by thermal oxidation carried out at low pressure and a layer of silicon nitride laid down on the tunneling layer by a low-pressure chemical vapor deposition, the interface of the two layers forming a charge storage area with the EAROM having improved read/write switching capability and quality, and improved reliability and memory retentivity characteristics.

BACKGROUND OF THE INVENTION

Electrically alterable read only memory (EAROM) semiconductors are usedas programmable non-volatile memory devices. Such memory devices in theform of individual memory cells can be laid down as part of anintegrated circuit chip (IC) in predetermined patterns with high densityat a relatively low cost. Such devices require low power and arerelatively simple to erase and write by applying appropriate voltages tothe gate electrode of the device. They have found widespread use in avariety of devices, for example, radio and television tuners, programstorage circuits, etc.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to an EAROM and, more particularly, to animproved EAROM of the metal-nitride-oxide semiconductor (MNOS) type. TheEAROM has improved quality and reliability and also has improvedoperating characteristics such as the ability to be switched through anerase/write cycle for a greater number of times than prior EAROM devicesand also, has a large time period of memory retentivity.

According to the invention, an EAROM device is provided which is made bya novel method. The method includes growing the tunneling, or gate,layer of insulating material, such as silicon dioxide, on the substrate(e.g., by a thermal oxidation reaction carried out at low pressure) andthereafter depositing a layer of charge storage material, such assilicon nitride, by low pressure chemical vapor deposition (LPCVD)rather than by a chemical vapor deposition process which is carried outat atmospheric pressure.

The memory retentivity characteristics of EAROM formed in this manner,with the tunneling layer of insulating material grown by thermaloxidation of the material with the substrate material, can becontrolled. The reliability of the device is also improved by layingdown of the charge storage layer by low pressure chemical vapordeposition.

OBJECTS

It therefore is an object of the present invention to provide animproved EAROM and a method of manufacturing the same.

An additional object is to provide an EAROM in which the insulatinglayer, or gate, is grown by a thermal oxidation reaction at lowpressure.

A further object is to provide an improved EAROM in which the layer ofcharge storage material is laid down by a low pressure chemical vapordeposition technique.

A further object of the invention is to provide an EAROM having asilicon dioxide-silicon nitride interface, with the silicon dioxidelayer being grown by a thermal reaction with the silicon substrate atlow pressure and the silicon nitride layer deposited by a low pressurechemical vapor deposition.

These and other objects and advantages of the present invention willbecome more apparent upon reference to the following specification andannexed drawings, in which:

DESCRIPTION OF DRAWINGS

FIG. 1 is an elevational view in cross-section of a completed EAROM madein accordance with the invention;

FIG. 2 is a schematic diagram of a furnace in which the EAROMs areprocessed;

FIG. 3 is a flow diagram showing the process of manufacturing thedevice;

FIG. 4 is a graph showing the relationship between retentivity and thepressure at which the silicon dioxide layer is grown; and

FIGS. 5A-E show the EAROM at various stages of the manufacturingprocess.

DETAILED DESCRIPTION

Referring to FIG. 1, a typical completed EAROM memory cell 10 made inaccordance with the invention is shown. The EAROM shown is of the PMNOSenhancement mode type although an NMNOS enhancement device also can bemade. It includes a substrate 12, of a suitable material, for example,silicon, which has been suitably doped with an N-type impurity, forexample, phosphorus. The impurity level can be, for example, in theorder of approximately 2×10¹⁵ atoms/cm. A pair of diffusion regions, orzones, 14,16 are formed on the top surface of the substrate to providethe source 14 which is doped with P type impurity and the drain 16 whichis also doped with P type impurity. The procedures for forming thesevarious diffusion zones are well known in the art and any conventionalprocess can be used. The source and drain diffusions can be, forexample, ion implanted boron having an impurity level in the order of10²⁰ atoms/cm³.

It should be understood that only one memory cell is being described. Anumber of such cells are generally formed on the substrate at the sametime, as is conventional in semiconductor manufacture.

The memory area is located between the source and drain diffusionregions. It is protected on each side by a field oxide barrier layer 21,for example, of silicon dioxide.

A memory cell 23 is formed on the substrate in the area between thebarrier layers 21. The cell includes a layer 24 of suitable insulatingmaterial, such as silicon dioxide (SiO₂), on the substrate. For purposesof illustration, layer 24 is shown with upstanding vertical walls 25forming a channel-shaped structure although these walls are not aspronounced in the actual structure. Layer 24 has a tunneling, or gate,portion 24b through which charges are to tunnel. As described below, thetunneling gate portion 24b is grown by a thermal chemical oxidationreaction with the substrate 12. On top of the SiO₂ layer 24 is depositeda charge storage layer 26 of an insulating material such as siliconnitride. As also described below, the charge storage layer 26 isdeposited by low-pressure chemical vapor deposition. A charge storagearea is formed at the interface of layers 24b and 26 as well as for acritical distance into the nitride layer.

Electrodes 18 and 20 are shown connected to the source and draindiffusion regions 14 and 16. These electrodes extend over the fieldoxide layers 21 and a layer of silicon nitride 22 is also preferablyinterposed between the two. A gate electrode 28 is connected to thenitride layer 26 to control the switching of the device. The electrodes18, 20 and 28 can be of any suitable material, for example, aluminum.Operating voltages are applied to the device by these electrodes.

The thinner part in the middle of the SiO₂ layer 24 is formed with achannel 29 in which the tunneling gate portion 24b is located. Thesilicon nitride layer 26 overlies gate 24b in channel 29. The thinnerSiO₂ thickness region is the memory gate region. In a typical device ithas a thickness of about 20 A°, although the range can be from about 10A° to about 35 A°. The remaining region of the interface is a non-memoryregion and has a thickness of about 400-500 A°, this thickness beingselected to control the switching characteristics of the cell.

In the operation of the EAROM in FIG. 1, consider that drain and source14,16 are at ground potential. If a voltage of the proper magnitude andpolarity is applied to the gate electrode 28, charges of the oppositepolarity will be attracted from the substrate. For example, considerthat a negative voltage is applied to the gate electrode 28. Thenegative voltage causes positive charge carriers (holes) from thesubstrate 12 to tunnel through the silicon dioxide tunneling layer 24and be trapped at the silicon dioxide-silicon nitride interface 27 inthe gate area 24b. Since both silicon dioxide and silicon nitride areextremely high quality insulators, the charge will remain trapped for anextremely long period of time.

The EAROM is "written" into the low conduction state (or turned "off")by the application of a negative voltage to the gate electrode 28. Thisproduces a net positive charge at the interface region. This charge hasthe same effect as a positive gate bias. It would oppose the fieldproduced by normal logic level negative signals applied to the gateelectrode.

The device is erased into a low threshold, or high conduction, state bythe application of a positive voltage to the gate electrode 28. Thispositive voltage attracts electrons to the interface 27 producing anegative charge. This negative bias aids negative logic signals appliedto the gate. In the erased state, the threshold may be so low that thedevice will always be "on". The low threshold erase state is determinedby the thickness of the non-memory, or greater thickness, portion of thelayer 24. That is, the thicker it is, the greater will be the magnitudeof negative voltage applied to gate electrode 28 needed to turn thedevice "on". A typical low threshold voltage is about -2 volts. The"off" (write) low conduction state voltage can be in the order of about-12 volts. The fairly large difference between the "on" and "off"threshold voltage permits reliable address decoding.

In determining the reliability and applicability of an EAROM device, twocharacteristics are often referred to. The first of these is theefficiency, or switching time, of the write/erase cycle and the secondis the duration of memory retentivity. As the thickness of the silicondioxide layer is decreased in the memory gate region, the switching timeis decreased by decreasing the distance of the charge injection path.This, however, decreases data retention time (retentivity) by allowingeasier charge dissipation through the silicon dioxide. The retentivitytime of a typical EAROM is typically given in years, with ten yearsbeing a not uncommon number. Increasing the density of the positivecharge carriers trapped at the interface 27 also allows faster writingand erasing, but creates dispersion paths through the nitride layerthereby decreasing the data retention time.

Another characteristic to be considered is the number of write/eraseswitching cycles that the device can tolerate before breaking down. Thenumber of such cycles is preferably made as great as possible. Anyimperfections in the quality of the layers 24b, 26, for example,non-uniform thicknesses, impurities, etc., will decrease the number ofwrite/erase cycles through which the device can be driven. Also, thereis a preferential tunneling effect whereby the silicon dioxide layerexperiences a greater debilitating effect during an erase cycle than awrite cycle. Non-uniformity in the layer further increases thedebilitating effect.

In a conventional EAROM manufacturing process, the nitride layer 26 islaid down by flowing gas at high pressure, usually at atmosphericpressure or slightly higher, into a vertical furnace. This processintroduces some non-uniformity in the deposition of the nitride layerresulting in a lower yield and also some marginality in memorycharacteristics.

FIG. 2 shows an apparatus and FIG. 3 a process for making the improvedEAROM, while FIGS. 5A to 5E show the EAROM at various stages of theprocess. In FIG. 2, a horizontal furnace 40 is shown. The furnace, whichcan be a quartz tube 42 around which heating coils, such resistanceheating coils (not shown) are wound, has a loading gate 43 with one ormore inlets 44 into which various gases can be introduced and one ormore outlets 45 which can be opened and closed by means of valves 46,47.The outlet 45 goes to a mechanical pump (not shown) of any suitableconfiguration. The devices of the invention can be made in a horizontalfurnace such as 42 which requires a smaller capital investment than avertical furnace and also permits more silicon blanks to be processed atthe same time with greater reproducibility and uniformity.

A number of pre-processed silicon wafers are loaded into the furnace. Asshown in FIG. 5A, these wafers have first been pre-processed to a pointwherein the source and drain diffusion regions 14, 16 have beencompleted and a silicon dioxide field layer 21a grown. Furtherpre-processing, as shown in FIG. 5B includes etching layer 21a to formthe field oxide barrier regions 21 and the vertical walls 25 for thememory cell region. As seen, a gap 24a is left to form the memorychannel region. The processing steps to this point in forming the blanksis conventional.

The wafers of FIG. 5B are loaded into the furnace. They are preferablystacked vertically with spacing therebetween to permit the gas to flowand the reaction to take place.

The processing steps are carried out as described with respect to theflow diagram of FIG. 3. After the wafers are loaded in step 50, furnacetube 42 is first purged with an inert gas, such as nitrogen, in step 52and is then evacuated.

The next step 54 is to pressurize the furnace tube with oxygen and thenin step 56 to flow oxygen at a relatively low pressure through thefurnace so that a thermal reaction, by thermal decomposition, isproduced with the substrate 12 thereby forming the silicon dioxide layeron the memory gate region 29 of the substrate. The thermal oxidation iscarried out at subatmospheric pressure, for example, at a pressure inthe range of from about 2 mm of Hg to about 500 mm of Hg and at atemperature from between about 625° C. to about 750° C.

FIG. 5C shows the device at the stage of the process wherein the memorygate tunneling layer 24b has been grown. As seen, the memory gatetunneling layer 24b is grown in the gap 24a (FIG. 5B) and is of lesserthickness than the remainder of layer 24. The function of the thickerportion of layer 24 was described previously.

In the prior art method for making EAROM's, the silicon dioxide memorygate layer 24b is also grown by thermal reaction of oxygen with thesilicon substrate but at atmospheric pressure. It has been found thatthe memory retentivity characteristics of an EAROM is directly relatedto the pressure at which the memory gate layer 24b is deposited. A graphof this relationship is shown in FIG. 4 where it is seen that theretentivity property given in terms of ΔV_(T) (change of electricallyalterable threshold voltage) in volts/decade increases with lowerpressures. Thus, to increase ΔV_(T), the oxidation reaction is carriedout at a lower pressure.

Thus, by controlling the pressure of the oxidation reaction, an EAROM isproduced whose retentivity characteristics can be controlled andimproved. It is believed that this feature has not heretofore beenrecognized.

In addition, the formation of the memory gate layer 24b is carried outat a much slower rate, since the pressure is lower, than would normallybe carried out when the pressure is approaching atmospheric pressure. Itappears that the oxidation at lower pressure allows a more completereaction, meaning that the silicon dioxide layer is more uniform. Thisresults in a device with better reliability.

After the oxidation reaction is concluded, the furnace tube is evacuatedand there is a nitrogen back fill 60 to flush the tube. A nitrogenannealing step takes place at 62 in which the charge density at theSi/SiO₂ interface due to oxidation is minimized. The nitrogen annealingis carried out at a temperature of about 700° C.

After the nitrogen annealing is completed, the furnace tube is againevacuated, leak checks are performed and the furnace tube againevacuated. In step 64 ammonia (NH₃) is flowed into the furnace at a lowrate and pressure before introducing the other gas, such as, forexample, dichlorosilane (SiH₂ Cl₂). The wafers soak in the ammonia gasfor a predetermined time. The flow of NH₃ and dichlorosilane gases isadjusted at 68 and the nitride deposition is carried out at step 70until the desired thickness of the nitride layer 26 is achieved.

The silicon nitride layer 26 is laid down by chemical vapor deposition.That is, there is a reaction of dichlorosilane with the ammonia toproduce silicon nitride. This is carried out at low pressure. Forexample, a typical operating range would be from about 50 um Hg to about50 mm Hg. The temperature of the furnace during the nitride depositionis in the range of from about 625° C. to about 750° C., with 700° C.being typical. The ratio of ammonia to silane in the range of about50/1. The thickness of the silicon nitride layer is about 500 °A toabout 600 °A.

The nitride deposition is carried out at a lower temperature thanusually used in the prior art, this generally being about 800° C. It hasbeen determined that there is a fairly linear relationship in the changeof retentivity properties (ΔV_(T) as measured in volts/decade) as afunction of the temperature at which the nitride layer is deposited. Thehigher the temperature, the greater will be ΔV_(T).

FIG. 5D shows the device after the deposition of the silicon nitridelayer 26. As can be seen layer 26 overlies the field barrier regions 21as well as filling in the gap between the top of the memory gate layer24b and the upper surface of the layer 24.

After a sufficient time has passed to achieve the desired thickness fornitride layer 26, the flow of the silane gas is turned off and there isa post-deposition purge 72 with ammonia. The post-deposition purgeensures that the reaction with dichlorosilane is complete so that thenitride layer is completely laid down.

The furnace tube is again evacuated and a further nitrogen backfill isadmitted at 74 into the tube. The tube is then subjected to a nitrogenannealing action at 78 again for the purpose of flushing any componentsof the chemical reaction and annealing out O_(ss). The furnace is thenevacuated and a nitrogen backfill takes place at 82. The work is thenremoved at 84. This completes the portion of the process carried out inthe furnace.

The wafers are then etched again to form openings to the source anddrain regions 14,16. This is shown in FIG. 5E. The electrodes are thenattached to give the completed device, shown in FIG. 1.

As seen, a novel EAROM device and method of manufacture has beendisclosed. By carrying out certain steps in the process of laying downthe layers of insulating material which form the memory cell, certain ofthe operating characteristics of the device can be controlled and theoverall quality of the device improved.

What is claimed is:
 1. A process of forming an electrically alterableread only memory semiconductor device comprising the steps offormingfirst and second spaced apart regions of a second conductivity type in asubstrate of a first conductivity type, growing a layer of a firstinsulating material on said substrate in the space between said firstand second regions, and depositing by chemical vapor deposition at apressure substantially lower than atmospheric pressure a layer of asecond insulating material of a higher dielectric constant than saidfirst material on said first layer.
 2. A process as in claim 1 whereinsaid first layer is grown by thermally reacting a gas with saidsubstrate.
 3. A process as in claim 2 wherein a gas is reacted with thesubstrate at a pressure substantially less than atmospheric to grow thefirst layer on the substrate.
 4. A process as in claim 3 wherein thesubstrate is silicon and to form the first layer the gas is oxygen, thereaction is carried out at a pressure in the range of from about 2 mm Hgto about 500 mm Hg at a temperature in the range of from about 625° C.to about 750° C., to form said first layer as silicon dioxide.
 5. Aprocess as in claim 4 wherein said second layer is deposited by flowinga gas containing the reactants for the material of the second layer overthe substrate having the first layer thereon at a pressure in the rangeof from about 50 um Hg to about 50 mm Hg.
 6. A process as in claim 5wherein the gas to form the second layer is dichlorosilane and ammoniato form said second layer as silicon nitride.
 7. A process as in claim 1wherein said second layer is deposited by flowing a gas containing thereactants for the material of the second layer over the substrate havingthe first layer thereon at a pressure in the range of from about 50 umHg to about 50 mm Hg.
 8. A process as in claim 7 wherein the gas isflowed at a pressure of about 30 mm Hg.
 9. A process as in claim 7wherein the gas is flowed at a temperature in the range of from about625° C. to about 750° C.
 10. A process as in claim 7 wherein the gas isdichlorosilane and ammonia to form said second layer as silicon nitride.11. A process of forming an electrically alterable read only memorysemiconductor device comprising the steps offorming first and secondspaced apart regions of a second conductivity type in a substrate ofsilicon of a first conductivity type, growing a layer of silicon dioxideinsulating material on said substrate in the space between said firstand second regions by flowing oxygen over said substrate at a pressurein the range of from about 2 mm Hg to about 500 mm Hg, and depositing onsaid first layer a layer of a first insulating material of a higherdielectric constant than said silicon dioxide layer.